1. Field
This patent document relates to semiconductor design technology and, more particularly, to a semiconductor memory device including a word line driving circuit and a method for detecting weak cells therein.
2. Description of the Related Art
Typically, after a semiconductor memory device is designed and fabricated, a test process at the wafer level and a test process at the package level are performed to determine whether the semiconductor memory device includes any chip fails.
During the wafer level test, a large amount of data is tested at a time through 64 or 128 parallel channels. Furthermore, since an operating frequency during the wafer level test is basically low, without considering an external noise or a noise caused by clock intervention, an external or internal voltage is lowered to perform the wafer level test.
When such a method is applied, most errors are detected. However, so-called weak cells of which one bit or several bits are dead due to charge sharing may not be detected.
Weak cells may occur as the chip density is gradually increased, the technology is more and more refined, and the operation voltage is gradually decreased. According to existing related art, since packaging is performed in a state where weak cells are not detected during the wafer level test, chip fails may still occur thus reducing the package yield.
Thus, research is being conducted on a variety of schemes for improving detection of weak cells.